NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1005 / 1379

PORTx_GPCHR field descriptions (continued)
Field Description
Selects which Pin Control Registers (31 through 16) bits [15:0] update with the value in GPWD. If a
selected Pin Control Register is locked then the write to that register is ignored.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
GPWD Global Pin Write Data
Write value that is written to all Pin Control Registers bits [15:0] that are selected by GPWE.
38.5.4 Global Interrupt Control Low Register (PORTx_GICLR)
Only 32-bit writes are supported to this register.
Address: Base a 88h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
GIWD GIWE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_GICLR field descriptions
Field Description
31–16
GIWD Global Interrupt Write Data
Write value that is written to all Pin Control Registers bits [31:16] that are selected by GIWE.
GIWE Global Interrupt Write Enable
Selects which Pin Control Registers (15 through 0) bits [31:16] update with the value in GIWD.
0 Corresponding Pin Control Register is not updated with the value in GPWD.
1 Corresponding Pin Control Register is updated with the value in GPWD.
38.5.5 Global Interrupt Control High Register (PORTx_GICHR)
Only 32-bit writes are supported to this register.
Address: Base a 8Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 0
W
GIWD GIWE
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 38 Port Control and Interrupts (PORT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1005