NXP Semiconductors K32 L2A Series, Reference Manual, Page: 113 / 1379

Table 5-1. Peripheral Clocks (continued)
Source Module Module Reset Bus Interface
Clock
Bus Interface
Clock Gating
Control
Peripheral
Functional Clock
PCCn Functional
Clock Divider
DMA channel
multiplexer
(DMAMUX) Chip Reset DIVSLOW_CLK Yes
AXBS Chip Reset DIVCORE_CLK
AIPS Chip Reset DIVCORE_CLK
INTMUX Chip Reset DIVSLOW_CLK
LLWU Chip Reset not
VLLS DIVSLOW_CLK LPO
SCG Chip Reset DIVSLOW_CLK
PCC Chip Reset DIVSLOW_CLK
PORT multiplex
control Chip Reset DIVSLOW_CLK Yes
SIM Chip Reset DIVSLOW_CLK
Power
Management
Controller (PMC) POR DIVSLOW_CLK
System Mode
Controller (SMC) Chip Reset not
VLLS DIVSLOW_CLK
Reset Control
Module (RCM) POR/LVD/VLLS DIVSLOW_CLK LPO
Security/Integrity
WDOG
1
Chip Reset DIVSLOW_CLK LPO, ERCLK,
SIRC
TRNG Chip Reset DIVSLOW_CLK Yes
CAU Chip Reset DIVCORE_CLK
CRC Chip Reset DIVSLOW_CLK Yes
Memory
Flash Memory Unit Early Reset
DIVSLOW_CLK Yes
Flash Memory
Controller Chip Reset DIVCORE_CLK
SRAM Chip Reset DIVCORE_CLK
System Register
File POR DIVSLOW_CLK
Analog
TSI
Chip Reset not
VLLS DIVSLOW_CLK Yes
ADC Chip Reset DIVSLOW_CLK Yes SCG DIV3
VREF Chip Reset DIVSLOW_CLK Yes
DAC Chip Reset DIVSLOW_CLK Yes
CMP Chip Reset DIVSLOW_CLK Yes
Timers
Table continues on the next page...
Chapter 5 Clock Distribution
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 113