NXP Semiconductors K32 L2A Series, Reference Manual, Page: 488 / 1379

EMVSIMx_CLKCFG field descriptions (continued)
Field Description
2 Divide by 2
>2 Non-zero value will divide clock accordingly
21.5.4 Baud Rate Divisor Register (EMVSIMx_DIVISOR)
This regiter configures the divisor value to generate the baud clock which will drive the
card clock and also generate the transmit and receive clocks and respective ETUs.
Address: 4004_E000h base + Ch offset = 4004_E00Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
DIVISOR_VALUE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 1 0 0
EMVSIMx_DIVISOR field descriptions
Field Description
31–9
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
DIVISOR_
VALUE
Divisor (F/D) Value
The value written to this register will be used to generate the ETU bit period that will be used by the
transmitter and receiver. The divisor value is the integer result of F/D value; where F and D are the clock
rate conversion integer and baud rate adjustment integer, respectively, that required for the desired
operation. The value in this register can be changed when no transaction is active with the smart card.
When programming this field, the fractional part of F/D should be rounded off the nearest integer.
0 - 4 Invalid. As per ISO 7816 specification, minimum value of F/D is 5
372 Divisor value for F = 372 and D = 1 (default)
others Integer value of result of F/D
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
488 NXP Semiconductors