NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1228 / 1379

48.1.3.3.11.1 Address
Register Offset Description
TRNG0_FRQCNT 400A501Ch Accessible at this address when
TRNG0_MCTL[PRGM] = 0]
48.1.3.3.11.2 Function
The TRNG0 Frequency Count Register is a read-only register used to read the frequency
counter within the TRNG entropy generator. It will read all zeroes unless
TRNG0_MCTL[TRNG_ACC] = 1. Note that this offset (0x1C) is used as
TRNG0_FRQMAX if TRNG0_MCTL[PRGM] is 1. If TRNG0_MCTL[PRGM] is 0, this
offset is used as TRNG0_FRQCNT readback register, as described here.
48.1.3.3.11.3 Diagram
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
Reserved
FRQ_CT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R FRQ_CT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
48.1.3.3.11.4 Fields
Field Function
31-22
—
Reserved. Always 0.
21-0
FRQ_CT
Frequency Count. If TRNG0_MCTL[TRNG_ACC] = 1, reads a sample frequency count taken during
entropy generation. Requires TRNG0_MCTL[PRGM] = 0. Note that if TRNG0_MCTL[PRGM] bit is 1, this
register address is used to access the Poker Test Maximum Limit in register TRNG0_PKRMAX, as
defined in the previous section.
48.1.3.3.12 TRNG0 Frequency Count Maximum Limit (TRNG0_FRQMAX)
Standalone True Random Number Generator (SA-TRNG).
K32 L2A Reference Manual, Rev. 2, 01/2020
1228 NXP Semiconductors