NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1330 / 1379

USBx_MISCCTRL field descriptions (continued)
Field Description
0 OWN error detect for ISO IN / ISO OUT is not disabled.
1 OWN error detect for ISO IN / ISO OUT is disabled.
1
SOFBUSSET
SOF_TOK Interrupt Generation Mode Select
This field is only valid for Host mode, that is, CTL[HOSTMODEEN]=1.
0 SOF_TOK interrupt is set according to SOF threshold value.
1 SOF_TOK interrupt is set when SOF counter reaches 0.
0
SOFDYNTHLD
Dynamic SOF Threshold Compare mode
This field is only valid for Host mode, that is, CTL[HOSTMODEEN]=1.
0 SOF_TOK interrupt is set when byte times SOF threshold is reached.
1 SOF_TOK interrupt is set when 8 byte times SOF threshold is reached or overstepped.
51.4.30 USB Clock recovery control (USBx_CLK_RECOVER_CTRL)
Signals in this register control the crystal-less USB clock mode in which the internal
FIRC oscillator is tuned to match the clock extracted from the incoming USB data
stream.
NOTE
The FIRC must be enabled in the SCG module.
Address: 4005_5000h base + 140h offset = 4005_5140h
Bit 7 6 5 4 3 2 1 0
Read
CLOCK_
RECOVER_
EN
RESET_
RESUME_
ROUGH_EN
RESTART_
IFRTRIM_
EN
Reserved Reserved Reserved Reserved
Write
Reset 0 0 0 0 0 0 0 0
USBx_CLK_RECOVER_CTRL field descriptions
Field Description
7
CLOCK_
RECOVER_EN
Crystal-less USB enable
This bit must be enabled if user wants to use the crystal-less USB mode for the Full Speed USB controller
and transceiver.
NOTE: This bit should not be set for USB host mode or OTG.
0 Disable clock recovery block (default)
1 Enable clock recovery block
6
RESET_
RESUME_
ROUGH_EN
Reset/resume to rough phase enable
The clock recovery block tracks the FIRC to get an accurate 48Mhz clock. It has two phases after user
enables clock_recover_en bit, rough phase and tracking phase. The step to fine tune the FIRC by
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1330 NXP Semiconductors