NXP Semiconductors K32 L2A Series, Reference Manual, Page: 767 / 1379

LPSPI memory map (continued)
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
400B_D000 Version ID Register (LPSPI1_VERID) 32 R 0100_0004h 29.2.1/767
400B_D004 Parameter Register (LPSPI1_PARAM) 32 R See section 29.2.2/768
400B_D010 Control Register (LPSPI1_CR) 32 R/W 0000_0000h 29.2.3/769
400B_D014 Status Register (LPSPI1_SR) 32 R/W 0000_0001h 29.2.4/770
400B_D018 Interrupt Enable Register (LPSPI1_IER) 32 R/W 0000_0000h 29.2.5/772
400B_D01C DMA Enable Register (LPSPI1_DER) 32 R/W 0000_0000h 29.2.6/773
400B_D020 Configuration Register 0 (LPSPI1_CFGR0) 32 R/W 0000_0000h 29.2.7/774
400B_D024 Configuration Register 1 (LPSPI1_CFGR1) 32 R/W 0000_0000h 29.2.8/775
400B_D030 Data Match Register 0 (LPSPI1_DMR0) 32 R/W 0000_0000h 29.2.9/777
400B_D034 Data Match Register 1 (LPSPI1_DMR1) 32 R/W 0000_0000h
29.2.10/
777
400B_D040 Clock Configuration Register (LPSPI1_CCR) 32 R/W 0000_0000h
29.2.11/
778
400B_D058 FIFO Control Register (LPSPI1_FCR) 32 R/W 0000_0000h
29.2.12/
779
400B_D05C FIFO Status Register (LPSPI1_FSR) 32 R 0000_0000h
29.2.13/
779
400B_D060 Transmit Command Register (LPSPI1_TCR) 32 R/W 0000_001Fh
29.2.14/
780
400B_D064 Transmit Data Register (LPSPI1_TDR) 32 W 0000_0000h
29.2.15/
783
400B_D070 Receive Status Register (LPSPI1_RSR) 32 R 0000_0002h
29.2.16/
784
400B_D074 Receive Data Register (LPSPI1_RDR) 32 R 0000_0000h
29.2.17/
785
29.2.1 Version ID Register (LPSPIx_VERID)
.
Address: Base a 0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
MAJOR MINOR FEATURE
W
Reset
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
LPSPIx_VERID field descriptions
Field Description
31–24
MAJOR
Major Version Number
Table continues on the next page...
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 767