NXP Semiconductors K32 L2A Series, Reference Manual, Page: 59 / 1379

3.4.7.3 Interrupt priority levels
This device supports 4 priority levels for interrupts. Therefore, in the NVIC, each source
in the IPR registers contains 2 bits. For example, IPR0 is shown below:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
IRQ3
0 0 0 0 0 0
IRQ2
0 0 0 0 0 0
IRQ1
0 0 0 0 0 0
IRQ0
0 0 0 0 0 0
W
3.4.7.4 Non-maskable interrupt
The non-maskable interrupt request to the NVIC is controlled by the external NMI signal.
The pin that the NMI0 signal is multiplexed on, must be configured for the NMI function,
to generate the non-maskable interrupt request.
• The Core enables the NMI in NVIC0 by default, and the NMI0 pin is also enabled by
default.
Asynchronous Wake-up Interrupt Controller (AWIC)
3.4.8.1 AWIC overview
The primary function of the AWIC block is to detect asynchronous wake-up events in
stop modes, and then signal to the clock control logic to resume system clocking. After
the clock restarts, the NVIC observes the pending interrupt and performs the normal
interrupt or event processing.
3.4.8.2 Wake-up sources
The device uses the following internal and external inputs to the AWIC module.
Table 3-7. AWIC stop wake-up sources
Wake-up source Description
Available system resets RESET_b pin when LPO is its clock source
Low-voltage detect Power management controller—functional in Stop mode
Low-voltage warning Power management controller—functional in Stop mode
Pin interrupts Port control module—any enabled pin interrupt is capable of waking the system.
ADC The ADC is functional when using internal clock source.
CMP Interrupt in normal or trigger mode
Table continues on the next page...
3.4.8
Chapter 3 Chip Configuration
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 59