NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1079 / 1379

SCG_FIRCCSR field descriptions (continued)
Field Description
24
FIRCVLD
Fast IRC Valid status
0 Fast IRC is not enabled or clock is not valid.
1 Fast IRC is enabled and output clock is valid. The clock is valid once there is an output clock from the
FIRC analog.
23
LK
Lock Register
This bit field can be cleared/set at any time.
0 Control Status Register can be written.
1 Control Status Register cannot be written.
22–10
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
9
FIRCTRUP
Fast IRC Trim Update
0 Disable Fast IRC trimming updates
1 Enable Fast IRC trimming updates
8
FIRCTREN
Fast IRC Trim Enable
0 Disable trimming Fast IRC to an external clock source
1 Enable trimming Fast IRC to an external clock source
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
FIRCREGOFF
Fast IRC Regulator Enable
NOTE: When Fast IRC is used, FIRCREGOFF must be 0. Fast IRC cannot be operated with
FIRCREGOFF=1.
0 Fast IRC Regulator is enabled.
1 Fast IRC Regulator is disabled.
2
FIRCLPEN
Fast IRC Low Power Enable
0 Fast IRC is disabled in VLP modes
1 Fast IRC is enabled in VLP modes
1
FIRCSTEN
Fast IRC Stop Enable
0 Fast IRC is disabled in Stop modes. When selected as the reference clock to the System PLL and if
the System PLL is enabled in STOP mode, the Fast IRC will stay enabled even if FIRCSTEN=0.
1 Fast IRC is enabled in Stop modes
0
FIRCEN
Fast IRC Enable
If this bit written during clock switching, it should be read back and confirmed before proceeding.
FIRCEN should not toggle when FIRCTREN = 1.
0 Fast IRC is disabled
1 Fast IRC is enabled
Chapter 42 System Clock Generator (SCG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1079