NXP Semiconductors K32 L2A Series, Reference Manual, Page: 669 / 1379

The external wakeup input pins can be enabled to detect either rising-edge, falling-edge,
or on any change.
Table 26-1. LLWU signal descriptions
Signal Description I/O
LLWU_Pn Wakeup inputs (n = 0- 31) I
26.3 Memory map/register definition
The LLWU includes the following registers:
• Wake-up source enable registers
• Enable external pin input sources
• Enable internal peripheral interrupt sources
• Enable internal peripheral DMA sources
• Wake-up flag registers
• Indication of wakeup source that caused exit from a low-leakage power mode
includes external pin or internal module interrupt
• Wake-up pin filter enable registers
NOTE
The LLWU registers can be written only in supervisor mode.
Write accesses in user mode are blocked and will result in a bus
error.
Registers for Pin/Module sources marked "Reserved" in the
LLWU chip configuration information will not be writable and
will return 0 when read.
All LLWU registers are reset by Chip Reset not VLLS and by
reset types that trigger Chip Reset not VLLS. Each register's
displayed reset value represents this subset of reset types.
LLWU registers are unaffected by reset types that do not trigger
Chip Reset not VLLS. For more information about the types of
reset on this chip, refer to the
Introduction details.
Chapter 26 Low-Leakage Wakeup Unit (LLWU)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 669