NXP Semiconductors K32 L2A Series, Reference Manual, Page: 661 / 1379

INTMUXx_CHn_VEC field descriptions
Field Description
31–14
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
13–2
VECN
Vector Number
These bits represent the vector number for the highest priority interrupt source of this channel.
VECN[13:2] = (CPU v NVIC vectors)
+ Number of the highest priority interrupt source of this channel.
NOTE: The interrupt priority is based on the Interrupt Pending Register. The smaller the
interrupt source number, the higher the priority.
Reserved This field is reserved.
This read-only field is reserved and always has the value 0.
25.2.3 Channel n Interrupt Enable Register
(INTMUXx_CHn_IER_31_0)
Address: 4002_4000h base + 10h (64d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INTE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
INTMUXx_CHn_IER_31_0 field descriptions
Field Description
INTE Interrupt Enable
These bits are used to enable the interrupt sources of this channel.
0 Interrupt is disabled.
1 Interrupt is enabled.
25.2.4 Channel n Interrupt Pending Register
(INTMUXx_CHn_IPR_31_0)
Address: 4002_4000h base + 20h (64d × i), where i=0d to 3d
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
INTP
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Chapter 25 Interrupt Multiplexer (INTMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 661