NXP Semiconductors K32 L2A Series, Reference Manual, Page: 437 / 1379

20.3.19 Hardware Request Status Register (DMAx_HRS)
The HRS register provides a bit map for the DMA channels, signaling the presence of a
hardware request for each channel. The hardware request status bits reflect the current
state of the register and qualified (via the ERQ fields) DMA request signals as seen by
the DMA’s arbitration logic. This view into the hardware request signals may be used for
debug purposes.
NOTE
These bits reflect the state of the request as seen by the
arbitration logic. Therefore, this status is affected by the ERQ
bits.
Address: 4000_8000h base + 34h offset = 4000_8034h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 HRS7 HRS6 HRS5 HRS4 HRS3 HRS2 HRS1 HRS0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DMAx_HRS field descriptions
Field Description
31–8
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
7
HRS7
Hardware Request Status Channel 7
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 7 is not present
1 A hardware service request for channel 7 is present
6
HRS6
Hardware Request Status Channel 6
The HRS bit for its respective channel remains asserted for the period when a Hardware Request is
Present on the Channel. After the Request is completed and Channel is free, the HRS bit is automatically
cleared by hardware.
0 A hardware service request for channel 6 is not present
1 A hardware service request for channel 6 is present
5
HRS5
Hardware Request Status Channel 5
Table continues on the next page...
Chapter 20 Enhanced Direct Memory Access (eDMA)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 437