NXP Semiconductors K32 L2A Series, Reference Manual, Page: 746 / 1379

28.1.2 Block Diagram
LPIT
IPS Bus
Interface
Global
Registers
Channel
Registers
Interrupt
Bus Clock
IPS Bus
Global
Synchronizers
Timer
Freeze
Trig Out 0
Pre-Trig Out 0
Low Power
Clock Gate
Timer Channel 0
Timer Channel 1
Timer Channel 2
Timer Channel n-1
Trig Out 1
Pre-Trig Out 1
Trig Out 2
Pre-Trig Out 2
Trig Out n-1
Pre-Trig Out n-1
Pre-Trig Out n
Trig Out n
Previous
Channel
Timeout
Channel
Registers
Async
IRQ bit
32-bit Counter
Trigger Out
Generation
Trigger Rising
Edge Trigger
Select
Logic that is in every Timer Channel
Counter
Control
Peripheral Clock
D Q
Q
Access
Interface
Async Reset
External Trigger Inputs
(per channel)
Sync'ed Reset to all Timer channels
Channel Registers
Access Synchronizer
Counter Value
Timeout
Load Enable
Sync'ed
External
Triggers
(per channel)
Timer Channel n
Figure 28-1. Top Level Block Diagram
28.2 Modes of operation
The LPIT module supports the chip modes described in the following table.
Table 28-1. Chip modes supported by the LPIT module
Chip mode LPIT Operation
Run Normal operation
Stop/Wait Can continue operating provided the Doze Enable bit (MCR[DOZE_EN]) is set and
the LPIT is using an external or internal clock source which remains operating
during stop/wait modes.
Low Leakage Stop The Doze Enable (MCR[DOZE_EN]) bit is ignored and the LPIT will be disabled for
the duration of low leakage mode.
Debug Can continue operating provided the Debug Enable bit (MCR[DBG_EN]) is set.
Modes of operation
K32 L2A Reference Manual, Rev. 2, 01/2020
746 NXP Semiconductors