NXP Semiconductors K32 L2A Series, Reference Manual, Page: 452 / 1379

DMAx_TCDn_CSR field descriptions (continued)
Field Description
0 The current channel’s TCD is normal format.
1 The current channel’s TCD specifies a scatter gather format. The DLASTSGA field provides a memory
pointer to the next TCD to be loaded into this channel after the major loop completes its execution.
3
DREQ
Disable Request
If this flag is set, the eDMA hardware automatically clears the corresponding ERQ bit when the current
major iteration count reaches zero.
0 The channel’s ERQ bit is not affected.
1 The channel’s ERQ bit is cleared when the major loop is complete.
2
INTHALF
Enable an interrupt when major counter is half complete.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT
register when the current major iteration count reaches the halfway point. Specifically, the comparison
performed by the eDMA engine is (CITER == (BITER >> 1)). This halfway point interrupt request is
provided to support double-buffered, also known as ping-pong, schemes or other types of data movement
where the processor needs an early indication of the transfer’s progress.
NOTE: If BITER = 1, do not use INTHALF. Use INTMAJOR instead.
0 The half-point interrupt is disabled.
1 The half-point interrupt is enabled.
1
INTMAJOR
Enable an interrupt when major iteration count completes.
If this flag is set, the channel generates an interrupt request by setting the appropriate bit in the INT when
the current major iteration count reaches zero.
0 The end-of-major loop interrupt is disabled.
1 The end-of-major loop interrupt is enabled.
0
START
Channel Start
If this flag is set, the channel is requesting service. The eDMA hardware automatically clears this flag after
the channel begins execution.
0 The channel is not explicitly started.
1 The channel is explicitly started via a software initiated service request.
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
452 NXP Semiconductors