NXP Semiconductors K32 L2A Series, Reference Manual, Page: 891 / 1379

Chapter 35
Micro Trace Buffer (MTB)
35.1 Introduction
Microcontrollers using the Cortex-M0+ processor core include support for a CoreSight
Micro Trace Buffer to provide program trace capabilities.
The proper name for this function is the CoreSight Micro Trace Buffer for the Cortex-
M0+ Processor; in this document, it is simply abbreviated as the MTB.
The simple program trace function creates instruction address change-of-flow data
packets in a user-defined region of the system RAM. Accordingly, the system RAM
controller manages requests from two sources:
• AMBA-AHB reads and writes from the system bus
• program trace packet writes from the processor
As part of the MTB functionality, there is a DWT (Data Watchpoint and Trace) module
that allows the user to define watchpoint addresses, or optionally, an address and data
value, that when triggered, can be used to start or stop the program trace recording.
This document details the functionality of both the MTB_RAM and MTB_DWT
capabilities.
35.1.1 Overview
A generic block diagram of the processor core and platform for this class of ultra low-end
microcontrollers is shown as follows:
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 891