NXP Semiconductors K32 L2A Series, Reference Manual, Page: 588 / 1379

Table 22-15. Motorola 68K/Intel 8080 Write Configuration (continued)
Register Value Comments
TIMCFG0 0x0000_2200 Configure enable on trigger high and
disable on compare. Timer output high
on enable.
TIMCTL0 0x01C3_1001 (Motorola 68K, 1-beat)
0x1DC3_1001 (Motorola 68K, 16-beats)
0x01C3_1081 (Intel 8080, 1-beat)
0x1DC3_1081 (Intel 8080, 16-beats)
Configure dual 8-bit counter using
FXIO_D[16] output (EN pin for 68K,
nWR pin for 8080), with Shifter 0 (1-
beat) or Shifter 7 (16-beats) flag as the
inverted trigger.
SHIFTBUF0...7 Data to transmit Transmit data can be written to
SHIFTBUF0 (1-beat) or SHIFTBUF0...7
(16-beats) to initiate a transfer, use the
Shifter Status Flag to indicate when data
can be written using interrupt or DMA
request.
Table 22-16. Motorola 68K/Intel 8080 Read Configuration
Register Value Comments
SHIFTCFG0...6 0x000F_0100 Configure 16-bit parallel shift in from
adjacent shifter.
SHIFTCFG7 0x000F_0000 Configure 16-bit parallel shift in from pin.
SHIFTCTL0...7 0x0080_0001 Configure receive using Timer 0 on
negedge of clock with data input from
FXIO_D[15:0].
TIMCMP0 0x0000_0101 (1-beat)
0x0000_1F01 (16-beats)
Configure 1 or 16-beat transfer with
baud rate of divide by 4 of the FlexIO
clock. Set TIMCMP[15:8] = (number of
beats x 2) - 1. Set TIMCMP[7:0] = (baud
rate divider / 2) - 1.
TIMCFG0 0x0000_2220 Configure stop_bit, enable on trigger
high and disable on compare. Timer
output high on enable.
TIMCTL0 0x1DC3_1001 (Motorola 68K, 1 beat)
0x01C3_1001 (Motorola 68K, 16 beats)
0x1DC3_1181 (Intel 8080, 1 beat)
0x01C3_1181 (Intel 8080, 16 beats)
Configure dual 8-bit counter using either
FXIO_D[16] output (EN pin for 68K) or
FXIO_D[17] output (nRD pin for 8080),
with Shifter 7 flag (1-beat) or Shifter 0
flag (16-beats) as the inverted trigger.
SHIFTBUF0...7 Data received Received data can be read from
SHIFTBUF0 (1-beat) or SHIFTBUF0...7
(16-beats), use the Shifter Status Flag to
indicate when data can be read using
interrupt or DMA request.
In general, any operation to a 68K/8080 bus slave will begin with a register write cycle
followed by one or more data read or write cycles. To accomplish this, the following
program flow should be used:
Application Information
K32 L2A Reference Manual, Rev. 2, 01/2020
588 NXP Semiconductors