NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1358 / 1379

• Provides robust check that program flow is faster than expected
• Early refresh attempts trigger a reset.
• Optional timeout interrupt to allow post-processing diagnostics
• Interrupt request to CPU with interrupt vector for an interrupt service routine
(ISR)
• Forced reset occurs 128 bus clocks after the interrupt vector fetch.
• Configuration bits are write-once-after-reset to ensure watchdog configuration cannot
be mistakenly altered.
• Robust write sequence for unlocking write-once configuration bits
• Unlock sequence of writing 0x20C5 and then 0x28D9 within 16 bus clocks for
allowing updates to write-once configuration bits
• Software must make updates within 128 bus clocks after unlocking and before
WDOG32 closes the unlock window.
54.1.2 Block diagram
The following figure shows a block diagram of the WDOG module.
MUX
MUX
MUX
ERCLK
SIRC
UPDATE EN
CLK PRES WIN INT
(1K CLK from PMC)
BUS CLK
256
16-bit Window Register
0x28D9
0x20C5 Control Status
128 Bus Cycle
Disable Protect
Bit Write Control
Protect
Window
Reset
Counter
Overflow
Counter
Write Control
0x02A6
0x80B4
16-bit Timeout Value Register
Refresh Sequence
Compare Logic
16-bit Counter Register
Compare Logic
Control
Logic
128 Bus
CPU Reset
IRQ Interrupt
Clock Delay
Backup Reset
(8 MHz IRC
(Slow clock)
LPO
from SCG)
(external ref clock
from SCG)
Figure 54-1. WDOG block diagram
Introduction
K32 L2A Reference Manual, Rev. 2, 01/2020
1358 NXP Semiconductors