NXP Semiconductors K32 L2A Series, Reference Manual, Page: 733 / 1379

• START or Repeated START condition with address byte and expecting ACK or
NACK.
• Transmit data (this is the default for zero extended byte writes to the transmit FIFO).
• Receive 1-256 bytes of data (can also be configured to discard receive data and not
store in receive FIFO).
• STOP condition (can also be configured to send STOP condition when transmit FIFO
is empty).
Multiple transmit and receive commands can be inserted between the START condition
and STOP conditon, transmit and receive commands must not be interleaved in order to
comply with the I2C specification. The receive data command and the receive data and
discard command can be interleaved to ensure only the desired received data is stored in
the receive FIFO (or compared with the data match logic).
The LPI2C master supports 10-bit addressing through a (repeated) START condition,
followed by a transmit byte with the second address byte, followed by any number of
data bytes with the master-transmit data.
A START or Repeated START condition that is expecting a NACK (for example, hs-
mode master code) must be followed by a STOP or (repeated) START condition.
27.3.2.2 Master Operation
Whenever the LPI2C is enabled, it monitors the I2C bus to detect when the I2C bus is
idle (MSR[BBF]). The I2C bus is no longer considered idle if either SCL or SDA are low
and becomes idle if a STOP condition is detected or if a bus idle timeout is detected (as
configured by MCFGR2[BUSIDLE]). Once the I2C bus is idle, the transmit FIFO is not
empty, and the host request is either asserted or disabled, then the LPI2C master will
initiate a transfer on the I2C bus. This involves the following steps:
• Wait the bus idle time equal to (MCCR0[CLKLO] + 1) multiplied by the prescaler.
• Transmit a START condition and address byte using the timing configuration in
MCCR0, if a high speed mode transfer is configured then timing configuration from
MCCR1 is used instead.
• Perform master-transmit or master-receive transfers, as configured by the transmit
FIFO.
• Transmit a Repeated START or STOP condition as configured by the transmit FIFO
and/or MCFGR1[AUTOSTOP]. A repeated START can change which timing
configuration register is used.
Chapter 27 Low Power Inter-Integrated Circuit (LPI2C)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 733