NXP Semiconductors K32 L2A Series, Reference Manual, Page: 558 / 1379

Field Function
The internal trigger selection is configured as follows:
• 4*N - Pin 2*N input
• 4*N+1 - Shifter N status flag
• 4*N+2 - Pin 2*N+1 input
• 4*N+3 - Timer N trigger output
23
TRGPOL
Trigger Polarity
0b - Trigger active high
1b - Trigger active low
22
TRGSRC
Trigger Source
0b - External trigger selected
1b - Internal trigger selected
21-18
—
17-16
PINCFG
Timer Pin Configuration
00b - Timer pin output disabled
01b - Timer pin open drain or bidirectional output enable
10b - Timer pin bidirectional output data
11b - Timer pin output
15-13
—
12-8
PINSEL
Timer Pin Select
Selects which pin is used by the Timer input or output. PINSEL=i will select the FXIO_Di pin.
7
PINPOL
Timer Pin Polarity
0b - Pin is active high
1b - Pin is active low
6-2
—
1-0
TIMOD
Timer Mode
In 8-bit counter mode, the lower 8-bits of the counter and compare register are used to configure the
baud rate of the timer shift clock and the upper 8-bits are used to configure the shifter bit count.
In 8-bit PWM mode, the lower 8-bits of the counter and compare register are used to configure the high
period of the timer shift clock and the upper 8-bits are used to configure the low period of the timer shift
clock. The shifter bit count is configured using another timer or external signal.
In 16-bit counter mode, the full 16-bits of the counter and compare register are used to configure either
the baud rate of the shift clock or the shifter bit count.
00b - Timer Disabled.
01b - Dual 8-bit counters baud/bit mode.
10b - Dual 8-bit counters PWM mode.
11b - Single 16-bit counter mode.
22.2.1.21 Timer Configuration N (TIMCFGa)
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
558 NXP Semiconductors