NXP Semiconductors K32 L2A Series, Reference Manual, Page: 832 / 1379

31.2.11 LPUART FIFO Register (LPUARTx_FIFO)
This register provides the ability for the programmer to turn on and off FIFO
functionality. It also provides the size of the FIFO that has been implemented. This
register may be read at any time. This register must be written only when CTRL[RE] and
CTRL[TE] are cleared/not set and when the data buffer/FIFO is empty.
Address: Base a 28h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
TXEMPT
RXEMPT
0
TXOF RXUF
W
w1c w1c
Reset 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R 0 0
0
RXIDEN
TXOFE
RXUFE
TXFE
TXFIFOSIZE
RXFE
RXFIFOSIZE
W
TXFLUSH
RXFLUSH
Reset
0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1
LPUARTx_FIFO field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23
TXEMPT
Transmit Buffer/FIFO Empty
Asserts when there is no data in the Transmit FIFO/buffer. This field does not take into account data that
is in the transmit shift register.
0 Transmit buffer is not empty.
1 Transmit buffer is empty.
Table continues on the next page...
Register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
832 NXP Semiconductors