NXP Semiconductors K32 L2A Series, Reference Manual, Page: 112 / 1379

5.3.3.10 SPLLDIV1_CLK
This output clock is fed from the SPLL, and is an optional functional clock for
peripherals.
For K32 L2A the SPLLDIV1_CLK is an optional peripheral functional clock for the
USB0 module only. It is selectable via the PCCUSB0 register.
5.3.3.11 SPLLDIV2_CLK
This output clock is fed from the SPLL, and is an optional functional clock for
peripherals.
For K32 L2A the FIRCDIV2_CLK is not implemented.
5.3.3.12 SPLLDIV3_CLK
This output clock is fed from the SPLL, and is an optional functional clock for
peripherals.
For K32 L2A the SPLLDIV3_CLK is an optional peripheral functional clock for various
timers and serial communication peripherals. It is selectable via the peripherals PCCn
register.
5.4 Peripheral Clock Summary
The SCG module supplies peripheral interface and functional clocks to the PCC,
depending on the peripheral. The peripheral interface clock can be either the
DIVCORE_CLK or the DIVSLOW_CLK, depending on the peripheral. The peripheral
functional clocks and the peripheral interface clocks for each module/peripheral are
detailed in table below.
Table 5-1. Peripheral Clocks
Source Module Module Reset Bus Interface
Clock
Bus Interface
Clock Gating
Control
Peripheral
Functional Clock
PCCn Functional
Clock Divider
System
Coretex M0+ Core
controller
Chip Reset DIVCORE_CLK
DMA controller Chip Reset DIVCORE_CLK Yes
Table continues on the next page...
Peripheral Clock Summary
K32 L2A Reference Manual, Rev. 2, 01/2020
112 NXP Semiconductors