NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1319 / 1379

USBx_CTL field descriptions (continued)
Field Description
3
HOSTMODEEN
When set to 1, this bit enables the USB Module to operate in Host mode. In host mode, the
USB module performs USB transactions under the programmed control of the host processor.
2
RESUME
When set to 1 this bit enables the USB Module to execute resume signaling. This allows the
USB Module to perform remote wake-up. Software must set RESUME to 1 for the required
amount of time and then clear it to 0. If HOSTMODEEN is set, the USB module appends a Low
Speed End of Packet to the Resume signaling when the RESUME bit is cleared.
1
ODDRST
Setting this bit to 1 resets all the BDT ODD ping/pong fields to 0, which then specifies the
EVEN BDT bank.
0
USBENSOFEN
USB Enable
Setting this bit enables the USB-FS to operate; clearing it disables the USB-FS. Setting the bit
causes the SIE to reset all of its ODD bits to the BDTs. Therefore, setting this bit resets much
of the logic in the SIE.
When host mode is enabled, clearing this bit causes the SIE to stop sending SOF tokens.
0 Disables the USB Module.
1 Enables the USB Module.
51.4.15 Address register (USBx_ADDR)
Holds the unique USB address that the USB module decodes when in Peripheral mode
(CTL[HOSTMODEEN]=0). When operating in Host mode (CTL[HOSTMODEEN]=1)
the USB module transmits this address with a TOKEN packet. This enables the USB
module to uniquely address any USB peripheral. In either mode, CTL[USBENSOFEN]
must be 1. The Address register is reset to 0x00 after the reset input becomes active or the
USB module decodes a USB reset signal. This action initializes the Address register to
decode address 0x00 as required by the USB specification.
Address: 4005_5000h base + 98h offset = 4005_5098h
Bit 7 6 5 4 3 2 1 0
Read
LSEN ADDR
Write
Reset 0 0 0 0 0 0 0 0
USBx_ADDR field descriptions
Field Description
7
LSEN
Low Speed Enable bit
Informs the USB module that the next token command written to the token register must be performed at
low speed. This enables the USB module to perform the necessary preamble required for low-speed data
transmissions.
ADDR USB Address
Table continues on the next page...
Chapter 51 Universal Serial Bus Full Speed OTG Controller (USBFSOTG)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1319