NXP Semiconductors K32 L2A Series, Reference Manual, Page: 837 / 1379

The central element of the LPUART transmitter is the transmit shift register that is 10-bit
to 13 bits long depending on the setting in the CTRL[M], BAUD[M10] and
BAUD[SBNS] control bits. For the remainder of this section, assume CTRL[M],
BAUD[M10] and BAUD[SBNS] are cleared, selecting the normal 8-bit data mode. In 8-
bit data mode, the shift register holds a start bit, eight data bits, and a stop bit. When the
transmit shift register is available for a new character, the value waiting in the transmit
data register is transferred to the shift register, synchronized with the baud rate clock, and
the transmit data register empty (STAT[TDRE]) status flag is set to indicate another
character may be written to the transmit data buffer at LPUART_DATA.
If no new character is waiting in the transmit data buffer after a stop bit is shifted out the
LPUART_TX pin, the transmitter sets the transmit complete flag and enters an idle
mode, with LPUART_TX high, waiting for more characters to transmit.
Writing 0 to CTRL[TE] does not immediately disable the transmitter. The current
transmit activity in progress must first be completed (that could include a data character,
idle character or break character), although the transmitter will not start transmitting
another character.
31.3.2.1 Send break and queued idle
The LPUART_CTRL[SBK] bit sends break characters originally used to gain the
attention of old teletype receivers. Break characters are a full character time of logic 0,
10-bit to 12-bit times including the start and stop bits. A longer break of 13-bit times can
be enabled by setting LPUART_STAT[BRK13]. Normally, a program would wait for
LPUART_STAT[TDRE] to become set to indicate the last character of a message has
moved to the transmit shifter, write 1, and then write 0 to the LPUART_CTRL[SBK] bit.
This action queues a break character to be sent as soon as the shifter is available. If
LPUART_CTRL[SBK] remains 1 when the queued break moves into the shifter,
synchronized to the baud rate clock, an additional break character is queued. If the
receiving device is another LPUART, the break characters are received as 0s in all data
bits and a framing error (LPUART_STAT[FE] = 1) occurs.
A break character can also be transmitted by writing to the LPUART_DATA register
with bit 13 set and the data bits clear. This supports transmitting the break character as
part of the normal data stream and also allows the DMA to transmit a break character.
When idle-line wakeup is used, a full character time of idle (logic 1) is needed between
messages to wake up any sleeping receivers. Normally, a program would wait for
LPUART_STAT[TDRE] to become set to indicate the last character of a message has
moved to the transmit shifter, then write 0 and then write 1 to the LPUART_CTRL[TE]
Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 837