NXP Semiconductors K32 L2A Series, Reference Manual, Page: 519 / 1379

21.6.4 EMV SIM Transmitter
The transmitter is responsible for reading the message bytes from the Tx FIFO, adding
the LRC or CRC at the end of the message block and re-transmit any byte on reception of
a NACK. It assists the receive operation by inserting NACKs when directed by the
receiver.
21.6.4.1 Message Transmission
The transmitter operation does not start until the Tx FIFO is empty. Software can
configure the EMV SIM module and enable the transmitter but unless a byte is written
into the Tx FIFO, no transmission will start. Clearing the XMT_EN bit while the
transmitter is in operation, will halt any transmission in progress, flush the transmit FIFO.
Refer
Message Handling section for more details on using the Tx FIFO.
The transmitter continuously transmits the messages from the Tx FIFO. Upon NACK
detection, the transmitter resends the same byte until the Transmitter NACK Threshold
limit is reached. When TNTE is set, the EMV SIM transmitter is halted, and all pending
transfers are aborted, and the TC, ETC, AND TFE flags are set. All bytes remaining in
the transmit FIFO are lost. There is no way to restart the transmission on the next byte in
the FIFO. The transmitter remains frozen until TNTE is cleared by software. The only
way to clear TNTE is to write a 1 to the TNTE bit in the TX_STATUS register. It is
possible to disable the detection of NACKs from the Smart Card by setting
TNCK_THD[3:0] to 0x0. By setting TNCK_THD[3:0] to 0x1, it is possible to disable all
retransmissions while still setting TNTE on the first NACK received. In general, TNTE is
set on the NACK that causes the threshold set by TNCK_THD[3:0] to be reached. This
final NACK will not cause a retransmission, whereas all previous NACKs will cause a
retransmission.
If all bytes are successfully transmitted and the Tx FIFO is empty, the transmitter send
the check byte (i.e. LRC or CRC) if the XMT_CRC_LRC and LRC_EN or CRC_EN bits
are set. The transmitter sends each byte to the LRC or CRC block to allow the check byte
generation.
At the end of each byte, the transmitter inserts the programmed Guard ETUs. Refer to
Protocol Timers section for more details on Guard Time Counter.
Chapter 21 Smart Card Interface Module (EMV SIM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 519