NXP Semiconductors K32 L2A Series, Reference Manual, Page: 155 / 1379

Table 9-5. MDM-AP Status register assignments (continued)
Bit Name Description
10 VLLSx Modes Exit This bit indicates an exit from VLLSx mode has occurred. The debugger
will lose communication while the system is in VLLSx (including access to
this register). After communication is reestablished, this bit indicates that
the system had been in VLLSx. Because the debug modules lose their
state during VLLSx modes, they need to be reconfigured.
This bit is set during the VLLSx recovery sequence. The VLLSx Mode Exit
bit is held until the debugger has had a chance to recognize that a VLLS
mode was exited, and is cleared by a write of 1 to the LLS, VLLSx Status
Acknowledge bit in MDM AP Control register.
11 – 15 Reserved for future use Always read 0.
16 CPU0 Core Halted Indicates that the CPU0 core has entered Debug Halt mode
17 CPU0 Core SLEEPDEEP Indicates the CPU0 core has entered a low-power mode
SLEEPING==1 and SLEEPDEEP==0 indicates wait or VLPW mode.
SLEEPING==1 and SLEEPDEEP==1 indicates stop or VLPS mode.
18 CPU0 Core SLEEPING
20 Reserved Reserved for future use
21 Reserved Reserved for future use
22 Reserved Reserved for future use
23 – 31 Reserved for future use Always read 0.
9.5 Debug resets
The debug system receives the following sources of reset:
• Debug reset (the CDBGRSTREQ field within the DP CTRL/STAT register) that
allows the debugger to reset the debug logic.
• System POR reset
Conversely, the debug system is capable of generating system reset using the following
mechanism:
• A system reset in the DAP control register which allows the debugger to hold the
system in reset.
• SYSRESETREQ field in the NVIC Application Interrupt and Reset control register
• A system reset in the DAP control register which allows the debugger to hold the
core in reset.
Chapter 9 Debug
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 155