NXP Semiconductors K32 L2A Series, Reference Manual, Page: 492 / 1379

EMVSIMx_CTRL field descriptions (continued)
Field Description
Used to enable/disable the clock input to the EMV SIM module. This bit will gate all clocks including the
Smart Card clock regardless of the state of the STOP bit described above.
Note: This bit will have no effect on the register read write clock. Only EMV SIM logic clock is gated.
0 EMV SIM input clock enabled (default)
1 EMV SIM input clock is disabled
10
SW_RST
Software Reset Bit
Used to reset the entire EMV SIM module. This acts the same as a hardware reset for the EMV SIM
module. This bit is self-clearing and always reads 0.
Note: Software should allow a minimum of 4 Protocol clock cycles before attempting to access the EMV
SIM module after a software reset.
0 EMV SIM Normal operation (default)
1 EMV SIM held in Reset
9
FLSH_TX
Flush Transmitter Bit
This bit operates as an EMV SIM transmitter reset. The receive portion of the EMV SIM module is not
affected. This bit clears automatically and always reads 0.
0 EMV SIM Transmitter normal operation (default)
1 EMV SIM Transmitter held in Reset
8
FLSH_RX
Flush Receiver Bit
This bit operates as an EMV SIM receiver reset. The transmit portion of the EMV SIM module is not
affected. This bits clears automatically and always reads 0.
0 EMV SIM Receiver normal operation (default)
1 EMV SIM Receiver held in Reset
7–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
ONACK
Overrun NACK Enable
Enables NACK generation when Rx FIFO is full and another message is ready for writing into the FIFO.
0 NACK generation on overrun is disabled (default)
1 NACK generation on overrun is enabled
2
ANACK
Auto NACK Enable
Enables NACK generation for parity errors in receieved messages or when invalid initial characters are
received in ICM mode.
0 NACK generation on errors disabled
1 NACK generation on errors enabled (default)
1
ICM
Initial Character Mode
Enables initial character mode. Will be automatically cleared by hardware once a valid initial character is
received.
0 Initial Character Mode disabled
1 Initial Character Mode enabled (default)
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
492 NXP Semiconductors