NXP Semiconductors K32 L2A Series, Reference Manual, Page: 140 / 1379

Depending on the stop requirements of the user application, a variety of stop modes are
available that provide state retention, partial power-down or full power-down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
For each run mode, there is a corresponding Wait and Stop mode. Wait modes are similar
to Arm Sleep modes. Stop modes (VLPS, STOP) are similar to Arm Sleep Deep mode.
The Very Low Power Run (VLPR) operating mode can drastically reduce runtime power
when the maximum bus frequency is not required to handle the application needs.
The three primary modes of operation are Run, Wait, and Stop. The WFI instruction
invokes both Wait and Stop modes for the chip. The primary modes are augmented in a
number of ways to provide lower power based on application needs.
Table 7-1. Chip power modes
Chip mode Description Core mode Normal
recovery
method
RUN (Normal
Run)
• Default mode out of reset
• On-chip voltage regulator is on. Run —
HRUN (High
Speed Run)
Allows maximum performance of chip.
• On-chip voltage regulator is on.
High Speed Run —
WAIT (Normal
Wait) - via WFI
Allows peripherals to function while the core is in Sleep mode,
reducing power.
• NVIC remains sensitive to interrupts
• Peripherals continue to be clocked.
Sleep Interrupt
STOP (Normal
Stop) - via WFI
Places chip in static state. Lowest power mode that retains all registers
while maintaining LVD protection.
• NVIC is disabled.
• AWIC is used to wake up from interrupt.
• Peripheral clocks are stopped.
Sleep Deep Interrupt
VLPR (Very
Low-Power Run)
On-chip voltage regulator is in a low-power mode that supplies only
enough power to run the chip at a reduced frequency.
• Reduced frequency Flash access mode (1 MHz)
• LVD off
Run —
VLPW (Very
Low-Power
Wait) -via WFI
Same as VLPR but with the core in Sleep mode to further reduce
power.
• NVIC remains sensitive to interrupts (FCLK = ON).
• On-chip voltage regulator is in a low-power mode that supplies
only enough power to run the chip at a reduced frequency.
Sleep Interrupt
VLPS (Very
Low-Power
Stop)-via WFI
Places chip in static state with LVD operation off. Lowest power mode
with ADC and pin interrupts functional.
• Peripheral clocks are stopped, but OSC, LPTMR,LPUART, RTC,
CMP, TSI can be used.
• TPM and UART can optionally be enabled if their clock source is
enabled.
• NVIC is disabled (FCLK = OFF); AWIC is used to wake up from
interrupt.
Sleep Deep Interrupt
Table continues on the next page...
Power modes
K32 L2A Reference Manual, Rev. 2, 01/2020
140 NXP Semiconductors