NXP Semiconductors K32 L2A Series, Reference Manual, Page: 51 / 1379

Chapter 3
Chip Configuration
3.1 Introduction
This chapter provides details on the individual modules of the microcontroller.
It includes:
• Module block diagrams showing immediate connections within the device
• Specific module-to-module interactions not necessarily discussed in the individual
module chapters
• Links for more information
In more detail:
• The device has 1 CPU (also called a core)
• Peripherals attached to the AIPS0 bridge are SoC-specific.
• The core and the DMAs have the capability to access peripherals on the AIPS0 and
AIPS1 bridges.
• The core and DMA0 can freely access all peripherals.
3.2 Clock gating
Peripherals on the AIPS0/AIPS1 bridges have clock gating capability via a Peripheral
Clock Control module (PCC).
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 51