NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1152 / 1379

46.3.11 Channel Trigger (TPMx_TRIG)
This register configures the trigger input for each channel.
Address: Base a 6Ch offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TRIG5 TRIG4 TRIG3 TRIG2 TRIG1 TRIG0
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_TRIG field descriptions
Field Description
31–6
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
5
TRIG5
Channel 5 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
4
TRIG4
Channel 4 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
3
TRIG3
Channel 3 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
2
TRIG2
Channel 2 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
1
TRIG1
Channel 1 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
0
TRIG0
Channel 0 Trigger
0 No effect.
1 The input trigger is used for input capture and modulates output (for output compare and PWM).
Memory Map and Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1152 NXP Semiconductors