NXP Semiconductors K32 L2A Series, Reference Manual, Page: 110 / 1379

and another group of peripherals to be clocked by another specific functional clock. E.g.
a group of low power peripherals would be clocked at a lower frequency than high
resolution timers or fast serial communication peripherals.
Each of these peripheral functional clocks has a programmable divider of the source
input, that is controlled within the SCG. Each of the peripheral functional clocks outputs,
after the SCG divider, are selectable via a peripheral’s PCCn register.
5.3.3.1 SOSCDIV1_CLK
This output clock is fed from the SOSC, and is an optional functional clock for
peripherals.
For K32 L2A, the SOSCDIV1_CLK is an optional peripheral functional clock for the
USB0 module only. It is selectable via the PCCUSB0 register.
5.3.3.2 SOSCDIV2_CLK
This output clock is fed from the SOSC, and is an optional functional clock for
peripherals.
For K32 L2A the SOSCDIV2_CLK is not implemented.
5.3.3.3 SOSCDIV3_CLK
This output clock is fed from the SOSC, and is an optional functional clock for
peripherals.
For K32 L2A the SOSCDIV3_CLK is an optional peripheral functional clock for various
timers and serial communication peripherals. It is selectable via the peripherals PCCn
register.
5.3.3.4 SIRCDIV1_CLK
This output clock is fed from the SIRC, and is an optional functional clock for
peripherals.
For K32 L2A the SIRCDIV1_CLK is an optional peripheral functional clock for the
USB0 module only. It is selectable via the PCCUSB0 register.
SCG Output Clocks
K32 L2A Reference Manual, Rev. 2, 01/2020
110 NXP Semiconductors