NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1145 / 1379

Address: Base a 14h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
COUNT
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_CNT field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
COUNT Counter value
46.3.6 Modulo (TPMx_MOD)
The Modulo register contains the modulo value for the TPM counter. When the TPM
counter reaches the modulo value and increments, the overflow flag (TOF) is set and the
next value of TPM counter depends on the selected counting method (see
Counter ).
Writing to the MOD register latches the value into a buffer. The MOD register is updated
with the value of its write buffer according to
MOD Register Update . Additional writes
to the MOD write buffer are ignored until the register has been updated.
It is recommended to initialize the TPM counter (write to CNT) before writing to the
MOD register to avoid confusion about when the first counter overflow will occur.
Address: Base a 18h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
MOD
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
TPMx_MOD field descriptions
Field Description
31–16
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
MOD Modulo value
This field must be written with single 16-bit or 32-bit access.
46.3.7 Capture and Compare Status (TPMx_STATUS)
The STATUS register contains a copy of the status flag, CnSC[CHnF] for each TPM
channel, as well as SC[TOF], for software convenience.
Chapter 46 Timer/PWM Module (TPM)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1145