NXP Semiconductors K32 L2A Series, Reference Manual, Page: 919 / 1379

For core configurations like that supported by Cortex-M0+, Arm recommends that a
debugger identifies and connects to the debug components using the CoreSight debug
infrastructure.
Arm recommends that a debugger follows the flow as shown in the following figure to
discover the components in the CoreSight debug infrastructure. In this case, a debugger
reads the peripheral and component ID registers for each CoreSight component in the
CoreSight system.
CoreSight access port
Base pointer
Redirection from the
System ROM table, if implemented
++
Flycatcher ROM table
CoreSight ID
Pointers
System control space
CoreSight ID
Flycatcher CPUID
Debug control
Data watchpoint unit
CoreSight ID
Watchpoint control
++
Breakpoint unit
CoreSight ID
Breakpoint control
++
Optional component
++
Figure 35-3. CoreSight discovery process
MTB_ROM memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
F000_2000 Entry (MTB0_ROM_ENTRY0) 32 R See section
35.3.3.1/
920
F000_2004 Entry (MTB0_ROM_ENTRY1) 32 R See section
35.3.3.1/
920
F000_2008 Entry (MTB0_ROM_ENTRY2) 32 R See section
35.3.3.1/
920
F000_200C Entry (MTB0_ROM_ENTRY3) 32 R See section
35.3.3.1/
920
F000_2010 End of Table Marker Register (MTB0_ROM_TABLEMARK) 32 R 0000_0000h
35.3.3.2/
921
F000_2FCC System Access Register (MTB0_ROM_SYSACCESS) 32 R 0000_0001h
35.3.3.3/
921
Table continues on the next page...
Chapter 35 Micro Trace Buffer (MTB)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 919