NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1154 / 1379

46.3.13 Filter Control (TPMx_FILTER)
This register selects the filter value of the channel inputs, and an additional output delay
value for the channel outputs. In PWM combine modes, the filter can effectively
implements deadtime insertion.
Address: Base a 78h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CH5FVAL CH4FVAL CH3FVAL CH2FVAL CH1FVAL CH0FVAL
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
TPMx_FILTER field descriptions
Field Description
31–24
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
23–20
CH5FVAL
Channel 5 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH5FVAL * 4) clock cycles.
19–16
CH4FVAL
Channel 4 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH4FVAL * 4) clock cycles.
15–12
CH3FVAL
Channel 3 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH3FVAL * 4) clock cycles.
11–8
CH2FVAL
Channel 2 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH2FVAL * 4) clock cycles.
7–4
CH1FVAL
Channel 1 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH1FVAL * 4) clock cycles.
CH0FVAL Channel 0 Filter Value
Selects the filter value for the channel input and the delay value for the channel output. The filter/delay is
disabled when the value is zero, otherwise the filter/delay is configured as (CH0FVAL * 4) clock cycles.
Memory Map and Register Definition
K32 L2A Reference Manual, Rev. 2, 01/2020
1154 NXP Semiconductors