NXP Semiconductors K32 L2A Series, Reference Manual, Page: 458 / 1379

1
eDMA Engine
Data Path
eDMA
0
Program Model/
64
Control
n-1
To/F
rom Cr
ossbar S
witch
2
Channel Arbitration
Address Path
Read Data
Write Data
Address
Read Data
Write Data
Write Address
eDMA Peripheral
Request
eDMA Done
Transfer
Control
Descriptor (TCD)
Int
er
nal P
er
ipher
al Bus
Figure 20-4. eDMA operation, part 3
20.4.2 Fault reporting and handling
Channel errors are reported in the Error Status register (DMAx_ES) and can be caused
by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
458 NXP Semiconductors