NXP Semiconductors K32 L2A Series, Reference Manual, Page: 432 / 1379

20.3.15 Clear Error Register (DMAx_CERR)
The CERR provides a simple memory-mapped mechanism to clear a given bit in the ERR
to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the ERR to be cleared. Setting the CAEI bit provides a
global clear function, forcing the ERR contents to be cleared, clearing all channel error
indicators. If the NOP bit is set, the command is ignored. This allows you to write
multiple-byte registers as a 32-bit word. Reads of this register return all zeroes.
Address: 4000_8000h base + 1Eh offset = 4000_801Eh
Bit 7 6 5 4 3 2 1 0
Read 0 0 0
Write NOP CAEI 0 CERR
Reset 0 0 0 0 0 0 0 0
DMAx_CERR field descriptions
Field Description
7
NOP
No Op enable
0 Normal operation
1 No operation, ignore the other bits in this register
6
CAEI
Clear All Error Indicators
0 Clear only the ERR bit specified in the CERR field
1 Clear all bits in ERR
5–3
Reserved
This field is reserved.
CERR Clear Error Indicator
Clears the corresponding bit in ERR
Memory map/register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
432 NXP Semiconductors