NXP Semiconductors K32 L2A Series, Reference Manual, Page: 775 / 1379

LPSPIx_CFGR0 field descriptions (continued)
Field Description
Configures the polarity of the host request pin.
0 Active low.
1 Active high.
0
HREN
Host Request Enable
When enabled in master mode, the LPSPI will only initiate a SPI bus transfer if the host request input is
asserted.
0 Host request is disabled.
1 Host request is enabled.
29.2.8 Configuration Register 1 (LPSPIx_CFGR1)
The CFGR1 should only be written when the LPSPI is disabled.
Address: Base a 24h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
PCSCFG OUTCFG
PINCFG
0
MATCFG
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
PCSPOL
0
NOSTALL
AUTOPCS
SAMPLE
MASTER
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPSPIx_CFGR1 field descriptions
Field Description
31–28
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
27
PCSCFG
Peripheral Chip Select Configuration
PCSCFG must be set if performing 4-bit transfers.
0 PCS[3:2] are enabled.
1 PCS[3:2] are disabled.
26
OUTCFG
Output Config
Configures if the output data is tristated between accesses (LPSPI_PCS is negated).
Table continues on the next page...
Chapter 29 Low Power Serial Peripheral Interface (LPSPI)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 775