NXP Semiconductors K32 L2A Series, Reference Manual, Page: 914 / 1379

MTBx0_DWT_FCT0 field descriptions (continued)
Field Description
35.3.2.5 MTB_DWT Comparator Function Register 1
(MTBx0_DWT_FCT1)
The MTBDWT_FCTn registers control the operation of comparator n. Since the
MTB_DWT only supports data value comparisons on comparator 0, there are several
fields in the MTBDWT_FCT1 register that are RAZ/WI (bits 12, 11:10, 8).
Address: F000_1000h base + 38h offset = F000_1038h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
MATCHED
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
FUNCTION
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTBx0_DWT_FCT1 field descriptions
Field Description
31–25
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
Table continues on the next page...
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
914 NXP Semiconductors