NXP Semiconductors K32 L2A Series, Reference Manual, Page: 924 / 1379

PCC - Peripheral Clock Muxing and Gating
Peripheral clock select
(PCS bits in
the Peripheral's
PCC register).
Peripheral Functional Clock
Clock
Divider
Clock Divider
only available for
certain peripherals
Clock Sources
from Clock Generator
Module
External
Peripheral-Specific
Clock Source
This clock is used by the Peripheral
Functional Logic
(example - derive baud rates)
Clock Divide
Control
(PCD bits in
the Peripheral's
PCC register).
Post-Divider Mux
Control
(Ext Clk selected
if PCS=000)
Clock Gate
Control
Clock
Gate
PCC Register values
& Test Control Signals
Peripheral Interface Clock
This clock is used by PCC
Control and Config Registers
Slow System Clock or Platform Clock
Figure 36-1. PCC Clock Source Selection and Gating
36.2 Memory map and register definition
Each peripheral has its own dedicated PCC Register, which controls the clock gating,
clock source and dividers for that specific peripheral.
PCC registers can only be written in supervisor mode.
NOTE
Write accesses to unused PCC registers are blocked and result
in a bus error.
Memory map and register definition
K32 L2A Reference Manual, Rev. 2, 01/2020
924 NXP Semiconductors