NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1007 / 1379

The digital filter configuration is valid in all digital pin muxing modes.
Address: Base a C0h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DFE
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_DFER field descriptions
Field Description
DFE Digital Filter Enable
The digital filter configuration is valid in all digital pin muxing modes. The output of each digital filter is
reset to zero at system reset and whenever the digital filter is disabled. Each bit in the field enables the
digital filter of the same number as the field.
0 Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
1 Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
38.5.8 Digital Filter Clock Register (PORTx_DFCR)
This register is read only for ports that do not support a digital filter.
The digital filter configuration is valid in all digital pin muxing modes.
Address: Base a C4h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
CS
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PORTx_DFCR field descriptions
Field Description
31–1
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
0
CS
Clock Source
The digital filter configuration is valid in all digital pin muxing modes. Configures the clock source for the
digital input filters. Changing the filter clock source must be done only when all digital filters are disabled.
0 Digital filters are clocked by the bus clock.
1 Digital filters are clocked by the LPO clock.
Chapter 38 Port Control and Interrupts (PORT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 1007