NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1174 / 1379

If the opposite edge appears on the input signal before it can be validated, the counter is
reset. At the next input transition, the counter starts counting again. Any pulse that is
shorter than the minimum value selected by (CHnFVAL[3:0] × 4 counter clocks) is
regarded as a glitch and is not passed through the filter. A timing diagram of the input
filter is shown in the following figure.
The filter function is disabled when CHnFVAL[3:0] bits are zero. In this case, the input
signal is delayed by 2 rising edges of the counter clock. If (CHnFVAL[3:0] ≠ 0000), then
the input signal is delayed by the minimum pulse width (CHnFVAL[3:0] × 4 system
clocks) plus a further 3 rising edges of the system clock: two rising edges to the
synchronizer, plus one more to the edge detector. In other words, CHnF is set (3 + 4 ×
CHnFVAL[3:0]) counter clock periods after a valid edge occurs on the channel input.
CHnFVAL[3:0] = 0010
(binary value)
channel (n) input
after the synchronizer
counter
filter output
counter clock divided by 4
Time
Figure 46-24. Channel input filter example
46.4.11 Deadtime insertion
The deadtime insertion is enabled in PWM combine modes when CHnFVAL is non-zero.
The deadtime delay that is used for each TPM channel is defined as (CHnFVAL[3:0] x
4).
The deadtime delay insertion ensures that no two complementary signals (channels (n)
and (n+1)) drive the active state at the same time.
If POL(n) = 0, POL(n+1) = 1, and the deadtime is enabled, then when the channel (n)
match (TPM counter = C(n)V) occurs, the channel (n) output remains at the low value
until the end of the deadtime delay when the channel (n) output is set. Similarly, when the
channel (n+1) match (TPM counter = C(n+1)V) occurs, the channel (n+1) output remains
at the low value until the end of the deadtime delay when the channel (n+1) output is set.
See the following figures.
If POL(n) = 1, POL(n+1) = 0, and the deadtime is enabled, then when the channel (n)
match (TPM counter = C(n)V) occurs, the channel (n) output remains at the high value
until the end of the deadtime delay when the channel (n) output is cleared. Similarly,
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1174 NXP Semiconductors