NXP Semiconductors K32 L2A Series, Reference Manual, Page: 979 / 1379

interrupt, which is enabled by setting LVDSC2[LVWIE]. If enabled, an LVW interrupt
request occurs when LVDSC2[LVWF] is set. LVDSC2[LVWF] is cleared by writing 1 to
LVDSC2[LVWACK].
LVDSC2[LVWV] selects one of the four trip voltages:
• Highest: V
LVW4
• Two mid-levels: V
LVW3
and V
LVW2
• Lowest: V
LVW1
37.4 High-voltage detect (HVD) system
This device includes a system to guard against high-voltage conditions on the VDD
supply.
The system is comprised of a HVD circuit with a user-selectable trip voltage: high
(V
HVDH
) or low (V
HVDL
). The trip voltage is selected by HVDSC1[HVDV]. The HVD is
disabled upon entering VLPx, LLS, and VLLSx modes.
A flag is available to indicate the status of the high-voltage detect system:
• The High Voltage Detect Flag in the High Voltage Status and Control 1 Register
(HVDSC1[HVDF]) operates in a level sensitive manner. HVDSC1[HVDF] is set
when the supply voltage rises above the selected trip point (VHVD).
HVDSC1[HVDF] is cleared by writing 1 to HVDSC1[HVDACK], but only if the
internal supply has returned below the trip point; otherwise, HVDSC1[LVDF]
remains set.
37.4.1 HVD reset operation
By setting HVDSC1[HVDRE], the HVD generates a reset upon detection of a high-
voltage condition. The high-voltage detection threshold is determined by
HVDSC1[HVDV]. After an HVD reset occurs, the HVD system holds the MCU in reset
until the supply voltage falls below this threshold. The LVD field in the SRS register of
the RCM module (RCM_SRS[LVD]) is set following an HVD reset.
Chapter 37 Power Management Controller (PMC)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 979