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35.3.1.4 MTB Base Register (MTBx_BASE)
The read-only MTB_BASE Register indicates where the RAM is located in the system
memory map. This register is provided to enable auto discovery of the MTB RAM
location by a debug agent, and is defined by a hardware design parameter.
Address: F000_0000h base + Ch offset = F000_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
* Notes:
x = Undefined at reset.
•
MTBx_BASE field descriptions
Field
Description
BASEADDR
BASEADDR
This value is defined (hardwired): 0x1FFF_8000 (Core 0)
35.3.1.5 Integration Mode Control Register (MTBx_MODECTRL)
This register enables the device to switch from a functional mode, or default behavior,
into integration mode. It is hardwired to specific values used during the auto-discovery
process by an external debug agent.
Address: F000_0000h base + F00h offset = F000_0F00h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R
W
Reset
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MTBx_MODECTRL field descriptions
Field
Description
MODECTRL
MODECTRL
Hardwired to 0x0000_0000
Chapter 35 Micro Trace Buffer (MTB)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors
903
Summary of Contents for K32 L2A Series
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Page 122: ...Flash Memory Clock K32 L2A Reference Manual Rev 2 01 2020 122 NXP Semiconductors...
Page 158: ...Debug and security K32 L2A Reference Manual Rev 2 01 2020 158 NXP Semiconductors...
Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...
Page 246: ...Application information K32 L2A Reference Manual Rev 2 01 2020 246 NXP Semiconductors...
Page 374: ...CMP Trigger Mode K32 L2A Reference Manual Rev 2 01 2020 374 NXP Semiconductors...
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