NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1010 / 1379

38.6.3 Global interrupt control
The two global interrupt control registers allow a single register write to update the upper
half of the pin control register on up to 16 pins, all with the same value.
The global interrupt control registers are designed to enable software to quickly configure
multiple pins within the one port for the same interrupt configuration. However, the pin
control functions cannot be configured using the global interrupt control registers.
The global interrupt control registers are write-only registers and always read as 0.
38.6.4 External interrupts
The external interrupt capability of the PORT module is available in all digital pin
muxing modes provided the PORT module is enabled.
Each pin can be individually configured for any of the following external interrupt
modes:
• Interrupt disabled, default out of reset
• Rising edge flag (for software polling)
• Falling edge flag (for software polling)
• Rising and falling edge flag (for software polling)
• Active high level peripheral trigger (status flag disabled)
• Active low level peripheral trigger (status flag disabled)
• Active high level sensitive interrupt
• Active low level sensitive interrupt
• Rising edge sensitive interrupt
• Falling edge sensitive interrupt
• Rising and falling edge sensitive interrupt
• Rising edge sensitive DMA request
• Falling edge sensitive DMA request
• Rising and falling edge sensitive DMA request
The interrupt status flag is set when the configured edge or level is detected on the pin or
at the output of the digital input filter, if the digital input digital filter is enabled. When
not in Stop mode, the input is first synchronized to the bus clock to detect the configured
level or edge transition.
The PORT module generates a single interrupt that asserts when the interrupt status flag
is set for any enabled interrupt for that port. The interrupt negates after the interrupt status
flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in
either the PORT_ISFR or PORT_PCRn registers.
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
1010 NXP Semiconductors