NXP Semiconductors K32 L2A Series, Reference Manual, Page: 1304 / 1379

The packet received may be larger than the negotiated MaxPacket size. Typically, this is
caused by a software bug. For DMA overrun errors due to oversized data packets, the
USB specification is ambiguous. It assumes correct software drivers on both sides.
NAKing the packet can result in retransmission of the already oversized packet data.
Therefore, in response to oversized packets, the USB core continues ACKing the packet
for non-isochronous transfers.
Table 51-6. USB responses to DMA overrun errors
Errors due to Memory Latency Errors due to Oversized Packets
Non-Acknowledgment (NAK) or Bus Timeout (BTO) — See
bit 4 in "Error Interrupt Status Register (ERRSTAT)" as
appropriate for the class of transaction. Continues acknowledging (ACKing) the packet for non-
isochronous transfers.
—
The data written to memory is clipped to the MaxPacket size
so as not to corrupt system memory.
The DMAERR bit is set in the ERRSTAT register for host and
device modes of operation. Depending on the values of the
INTENB and ERRENB register, the core may assert an
interrupt to notify the processor of the DMA error. Asserts ERRSTAT[DMAERR] ,which can trigger an interrupt
and TOKDNE interrupt fires. Note: The TOK_PID field of the
BDT is not 1111 because the DMAERR is not due to latency.
• For host mode, the TOKDNE interrupt is generated and
the TOK_PID field of the BDT is 1111 to indicate the
DMA latency error. Host mode software can decide to
retry or move to next scheduled item.
• In device mode, the BDT is not written back nor is the
TOKDNE interrupt triggered because it is assumed that
a second attempt is queued and will succeed in the
future.
The packet length field written back to the BDT is the
MaxPacket value that represents the length of the clipped
data actually written to memory.
From here, the software can decide an appropriate course of action for future transactions such as stalling the endpoint,
canceling the transfer, disabling the endpoint, etc.
51.4 Memory map/Register definitions
This section provides the memory map and detailed descriptions of all USB interface
registers.
USB memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4005_5000 Peripheral ID register (USB0_PERID) 8 R 04h 51.4.1/1307
4005_5004 Peripheral ID Complement register (USB0_IDCOMP) 8 R FBh 51.4.2/1307
4005_5008 Peripheral Revision register (USB0_REV) 8 R 33h 51.4.3/1308
4005_500C Peripheral Additional Info register (USB0_ADDINFO) 8 R 01h 51.4.4/1308
4005_5010 OTG Interrupt Status register (USB0_OTGISTAT) 8 R/W 00h 51.4.5/1309
4005_5014 OTG Interrupt Control register (USB0_OTGICR) 8 R/W 00h 51.4.6/1310
Table continues on the next page...
Memory map/Register definitions
K32 L2A Reference Manual, Rev. 2, 01/2020
1304 NXP Semiconductors