NXP Semiconductors K32 L2A Series, Reference Manual, Page: 811 / 1379

M
PE
PT
RE
VARIABLE 12-BIT RECEIVE
S
T
O
P
S
T
A
R
T
RECEIVE
WAKEUP
DATA BUFFER
INTERNAL BUS
SBR12:0
BAUDRATE
CLOCK
RAF
LOGIC
SHIFT DIRECTION
ACTIVE EDGE
DETECT
LBKDE
MSBF
GENERATOR
SHIFT REGISTER
M10
RXINV
IRQ / DMA
LOGIC
DMA Requests
IRQ Requests
PARITY
LOGIC
CONTROL
RxD
RxD
LOOPS
RSRC
From Transmitter
RECEIVER
SOURCE
CONTROL
MODULE
ASYNCH
Figure 31-2. LPUART receiver block diagram
31.2 Register definition
The LPUART includes registers to control baud rate, select LPUART options, report
LPUART status, and for transmit/receive data. Access to an address outside the valid
memory map will generate a bus error.
LPUART memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4004_6000 Version ID Register (LPUART2_VERID) 32 R 0400_0003h 31.2.1/813
4004_6004 Parameter Register (LPUART2_PARAM) 32 R See section 31.2.2/813
4004_6008 LPUART Global Register (LPUART2_GLOBAL) 32 R/W 0000_0000h 31.2.3/814
4004_600C LPUART Pin Configuration Register (LPUART2_PINCFG) 32 R/W 0000_0000h 31.2.4/814
4004_6010 LPUART Baud Rate Register (LPUART2_BAUD) 32 R/W 0F00_0004h 31.2.5/815
4004_6014 LPUART Status Register (LPUART2_STAT) 32 R/W 00C0_0000h 31.2.6/818
4004_6018 LPUART Control Register (LPUART2_CTRL) 32 R/W 0000_0000h 31.2.7/822
4004_601C LPUART Data Register (LPUART2_DATA) 32 R/W 0000_1000h 31.2.8/827
4004_6020 LPUART Match Address Register (LPUART2_MATCH) 32 R/W 0000_0000h 31.2.9/829
Table continues on the next page...
Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 811