NXP Semiconductors K32 L2A Series, Reference Manual, Page: 815 / 1379

LPUARTx_PINCFG field descriptions (continued)
Field Description
Configures the input trigger usage.
00 Input trigger is disabled.
01 Input trigger is used instead of RXD pin input.
10 Input trigger is used instead of CTS pin input.
11 Input trigger is used to modulate the TXD pin output.
31.2.5 LPUART Baud Rate Register (LPUARTx_BAUD)
Address: Base a 10h offset
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
MAEN1 MAEN2
M10 OSR
TDMAE
0
RDMAE
0
MATCFG
BOTHEDGE
RESYNCDIS
W
Reset
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
LBKDIE
RXEDGIE
SBNS SBR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
LPUARTx_BAUD field descriptions
Field Description
31
MAEN1
Match Address Mode Enable 1
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA1].
30
MAEN2
Match Address Mode Enable 2
0 Normal operation.
1 Enables automatic address matching or data matching mode for MATCH[MA2].
29
M10
10-bit Mode select
The M10 bit causes a tenth bit to be part of the serial transmission. This bit should only be changed when
the transmitter and receiver are both disabled.
0 Receiver and transmitter use 8-bit or 9-bit data characters.
1 Receiver and transmitter use 10-bit data characters.
28–24
OSR
Oversampling Ratio
Table continues on the next page...
Chapter 31 Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 815