NXP Semiconductors K32 L2A Series, Reference Manual, Page: 340 / 1379

Table 15-7. Hash Function codes (continued)
HFx code HFx define Hash Function Hash logic
2 HFH MD5 H(), SHA Parity() CA1 ^ CA2 ^ CA3
3 HFI MD5 I() CA2 ^ (CA1 | CA3)
4 HFC SHA Ch() (CA1 & CA2) ^ (CA1 & CA3)
5 HFM SHA Maj() (CA1 & CA2) ^ (CA1 & CA3) ^ (CA2 & CA3)
6 HF2C SHA-256 Ch() (CA4 & CA5) ^ (CA1 & CA6)
7 HF2M SHA-256 Maj() (CA0 & CA1) ^ (CA0 & CA2) ^ (CA1 & CA2)
8 HF2S SHA-256 Sigma 0 ROTR
2
(CA0) ^ ROTR
13
(CA0) ^ ROTR
22
(CA0)
9 HF2T SHA-256 Sigma 1 ROTR
6
(CA4) ^ ROTR
11
(CA4) ^ ROTR
25
(CA4)
A HF2U SHA-256 Sigma 0 ROTR
7
(CA8) ^ ROTR
18
(CA8) ^ SHR
3
(CA8)
B HF2V SHA-256 Sigma 1 ROTR
17
(CA8) ^ ROTR
19
(CA8) ^ SHR
10
(CA8)
15.6.3.20 Secure Hash Shift (SHS)
The SHS command does a set of parallel register-to-register move and shift operations
for implementing SHA-1. The following source and destination assignments are made:
Register Value prior to command Value after command executes
CA4 CA4 CA3
CA3 CA3 CA2
CA2 CA2 CA1<<<30
CA1 CA1 CA0
CA0 CA0 CAA
CAA CAA CAA<<<5
15.6.3.21 Message Digest Shift (MDS)
The MDS command does a set of parallel register-to-register move operations for
implementing MD5. The following source and destination assignments are made:
Register Value prior to command Value after command executes
CA3 CA3 CA2
CA2 CA2 CA1
CA1 CA1 CAA
CAA CAA CA3
Functional description
K32 L2A Reference Manual, Rev. 2, 01/2020
340 NXP Semiconductors