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The entire flash storage capacity is partitioned into equal sized segments. Two registers
include a supervisor-only access control indicator and a execute-only access control
indicator for each segment.
The FAC logic performs the required access control evaluation using the reference
address and a 2-bit attribute (or "protection" field) as inputs from the bus cycle plus the
contents of the programming model registers.
The following code example illustrates C code for FAC evaluation:
unsigned long long sacc; // supervisor-only map
unsigned long long xacc; // execute-only map
unsigned int seg_size; // 8-bit segment size
unsigned int fac_error;
fac_evaluation (addr, prot)
unsigned int addr; // access address
unsigned int hprot; // encoded 2-bit "protection" field {supv, data}
{
unsigned int sacc_flag; // sacc flag for this segment
unsigned int xacc_flag; // xacc flag for this segment
unsigned int i; // segment index
i = (addr >> (8 + seg_size & 0x0f)) & 0x3f; // form 6-bit segment index
sacc_flag = (sacc >> i) & 1; // extract sacc bit for this segment
xacc_flag = (xacc >> i) & 1; // extract xacc bit for this segment
// create a 4-tuple concatenating the 2-bit protection field + {sacc, xacc} flags
switch ((hprot & 3) << 2 | (sacc_flag << 1) | xacc_flag) {
// all these combinations are allowed accesses
case 0x2: // {user, ifetch} && {supv+user, ifetch-only}
case 0x3: // {user, ifetch} && {supv+user, data}
case 0x7: // {user, data} && {supv+user, data}
case 0x8: // {supv, ifetch} && {supv-only, ifetch-only}
case 0x9: // {supv, ifetch} && {supv-only, data}
case 0xa: // {supv, ifetch} && {supv+user, ifetch-only}
case 0xb: // {supv, ifetch} && {supv+user, data}
case 0xd: // {supv, data} && {supv-only, data}
case 0xf: // {supv, data} && {supv+user, data}
fac_error = 00;
break;
// all these combinations are unallowed, that is, errored accesses
case 0x0: // {user, ifetch} && {supv-only, ifetch-only}
case 0x1: // {user, ifetch} && {supv-only, data}
case 0x4: // {user, data} && {supv-only, ifetch-only}
case 0x5: // {user, data} && {supv-only, data}
case 0x6: // {user, data} && {supv+user, ifetch-only}
case 0xc: // {supv, data} && {supv-only, ifetch-only}
case 0xe: // {supv, data} && {supv+user, ifetch-only}
fac_error = 1;
break;
} // switch()
} // fac_evaluation()
Flash Access Control (FAC) Function
K32 L2A Reference Manual, Rev. 2, 01/2020
600
NXP Semiconductors
Summary of Contents for K32 L2A Series
Page 2: ...K32 L2A Reference Manual Rev 2 01 2020 2 NXP Semiconductors...
Page 42: ...K32 L2A Reference Manual Rev 2 01 2020 42 NXP Semiconductors...
Page 122: ...Flash Memory Clock K32 L2A Reference Manual Rev 2 01 2020 122 NXP Semiconductors...
Page 158: ...Debug and security K32 L2A Reference Manual Rev 2 01 2020 158 NXP Semiconductors...
Page 174: ...Module Signal Description Tables K32 L2A Reference Manual Rev 2 01 2020 174 NXP Semiconductors...
Page 246: ...Application information K32 L2A Reference Manual Rev 2 01 2020 246 NXP Semiconductors...
Page 374: ...CMP Trigger Mode K32 L2A Reference Manual Rev 2 01 2020 374 NXP Semiconductors...
Page 384: ...Functional description K32 L2A Reference Manual Rev 2 01 2020 384 NXP Semiconductors...
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