NXP Semiconductors K32 L2A Series, Reference Manual, Page: 750 / 1379

LPITx_MCR field descriptions (continued)
Field Description
Enables the peripheral clock to the module timers. M_CEN bit must be asserted when writing to timer
registers. Both clocks (bus clock and peripheral clock) must be enabled, to allow for clock synchronization
and update of register bits.
NOTE: Writing to the MSR, SETTEN , CLRTEN, TCTRL, and TVAL registers while M_CEN = 0, will lead
to the assertion of a transfer error for that bus cycle. Writing to CVAL and reserved registers will
always generate a transfer error.
0 Protocol clock to timers is disabled
1 Protocol clock to timers is enabled
28.3.4 Module Status Register (LPITx_MSR)
Address: 4003_0000h base + Ch offset = 4003_000Ch
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0 TIF3 TIF2 TIF1 TIF0
W
w1c w1c w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_MSR field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
TIF3
Channel 3 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
2
TIF2
Channel 2 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
1
TIF1
Channel 1 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
Table continues on the next page...
Memory Map and Registers
K32 L2A Reference Manual, Rev. 2, 01/2020
750 NXP Semiconductors