NXP Semiconductors K32 L2A Series, Reference Manual, Page: 751 / 1379

LPITx_MSR field descriptions (continued)
Field Description
0 Timer has not timed out
1 Timeout has occurred
0
TIF0
Channel 0 Timer Interrupt Flag
In compare modes, sets to 1 at the end of the timer period. In capture modes, sets to 1 when the trigger
asserts. Writing logic 1 to this flag clears it. Writing 0 has no effect.
0 Timer has not timed out
1 Timeout has occurred
28.3.5 Module Interrupt Enable Register (LPITx_MIER)
Address: 4003_0000h base + 10h offset = 4003_0010h
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
0
TIE3 TIE2 TIE1 TIE0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
LPITx_MIER field descriptions
Field Description
31–4
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
3
TIE3
Channel 3 Timer Interrupt Enable
Enables interrupt generation when this bit is set to 1 and if corresponding Timer Interrupt Flag is asserted.
0 Interrupt generation is disabled
1 Interrupt generation is enabled
2
TIE2
Channel 2 Timer Interrupt Enable
Enables interrupt generation when this bit is set to 1 and if corresponding Timer Interrupt Flag is asserted.
0 Interrupt generation is disabled
1 Interrupt generation is enabled
1
TIE1
Channel 1 Timer Interrupt Enable
Enables interrupt generation when this bit is set to 1 and if corresponding Timer Interrupt Flag is asserted.
0 Interrupt generation is disabled
1 Interrupt generation is enabled
Table continues on the next page...
Chapter 28 Low Power Interrupt Timer (LPIT)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 751