NXP Semiconductors K32 L2A Series, Reference Manual, Page: 397 / 1379

In this mode, the DMA channel is disabled. Because disabling and enabling of DMA
channels is done primarily via the DMA configuration registers, this mode is used
mainly as the reset state for a DMA channel in the DMA channel MUX. It may also
be used to temporarily suspend a DMA channel while reconfiguration of the system
takes place, for example, changing the period of a DMA trigger.
• Normal mode
In this mode, a DMA source is routed directly to the specified DMA channel. The
operation of the DMAMUX in this mode is completely transparent to the system.
• Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a
transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done in the registers of the periodic interrupt timer
(LPIT). This mode is available only for channels 0–3.
19.2 External signal description
The DMAMUX has no external pins.
19.3 Memory map/register definition
This section provides a detailed description of all memory-mapped registers in the
DMAMUX.
DMAMUX memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4002_1000 Channel Configuration register (DMAMUX0_CHCFG0) 8 R/W 00h 19.3.1/398
4002_1001 Channel Configuration register (DMAMUX0_CHCFG1) 8 R/W 00h 19.3.1/398
4002_1002 Channel Configuration register (DMAMUX0_CHCFG2) 8 R/W 00h 19.3.1/398
4002_1003 Channel Configuration register (DMAMUX0_CHCFG3) 8 R/W 00h 19.3.1/398
4002_1004 Channel Configuration register (DMAMUX0_CHCFG4) 8 R/W 00h 19.3.1/398
4002_1005 Channel Configuration register (DMAMUX0_CHCFG5) 8 R/W 00h 19.3.1/398
4002_1006 Channel Configuration register (DMAMUX0_CHCFG6) 8 R/W 00h 19.3.1/398
4002_1007 Channel Configuration register (DMAMUX0_CHCFG7) 8 R/W 00h 19.3.1/398
Chapter 19 Direct Memory Access Multiplexer (DMAMUX)
K32 L2A Reference Manual, Rev. 2, 01/2020
NXP Semiconductors 397